Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 90 nm feature sizes. Fabrication of electronics devices typically entails designing components defined by a multitude of microelectronic circuits. Using fabrication technology, several microcircuits can be integrated on a single chip to form an integrated circuit (“IC”).
Formation of interconnects between various regions of an IC circuit is a conventional and necessary step of design and fabrication process. The interconnects are coated with one or more layers, including dielectric layers, in subsequent steps of the fabrication process. Because the interconnects often protrude from the surface of the substrate, the subsequently coated layers will have an uneven surface. When subjected to a chemical mechanical polishing process, the unevenness creates a pattern which can have considerable undesirable effects in the manufactured product. The unevenness in effective pattern density often results in uneven post-polish film thickness.
To assess the effect of the various layout features on how the region polishes over time a pattern density map is typically constructed. The pattern density map defines how the neighboring features of a particular region of the substrate affect how that region polishes over time. To take into consideration the actual pressure distribution of the CMP polish pad, the neighboring features have to be weighted appropriately when assessing the region's density. The effective density map is conventionally produced by first partitioning the global layout into local cells and then using a filter to weight the effect of local density for each cell. The effective density maps are particularly useful in predicting the polish response of the coated IC.
The conventional methods for addressing the uneven effective pattern density include reverse etch-back and dummy fill. In reverse etch-back the film thickness in areas of high density with large spans of raised areas is reduced by etching in order to form an even film (“planarization”). The dummy fill method a layout step is added to the design process by modifying the circuit layout to include fill structures which act to raise the density of the low density regions. The fill structure, also called dummy fills, serves no electrical or electronic function; rather they are added to level the unevenness in the subsequent layers. In other words, the additional features provided by the dummy fills raise the density of a specific region of the layout to make it on par with the balance of the IC.
Conventional dummy fills are defined by a single dummy feature arranged over the entire layout in an array which excludes the regions featuring the actual interconnect(s). The exact shape and dimensions of the dummy structure is often dictated by the design rules of the underlying layout. An algorithm that analyzes the original layout pattern density distribution and devises a fill structure for minimize the resulting effective pattern distribution of the layout is a smart dummy fill.
In addition, the conventional technology uses dummy patterns with identical shape and dimension. The fill dummy is repeated in an array to form a complete pattern. The repeating units of the conventional dummy pattern structure may comprise of different shapes such as square- or rectangular-shaped fills. FIGS. 1A–1D schematically represent conventional dummy fill structures. Specifically, each of FIGS. 1A, 1B and 1C show a different unit dummy shape. FIG. 1D shows conventional pattern structure 100 with dummy patterns 100 scattered throughout the substrate. The conventional methods used a repeating pattern to fill the blank regions (interchangeably, “extended regions”) of the substrate. For example, in FIG. 1B, a repeating square pattern is used to fill the extended regions of the substrate. In FIG. 1C, abutting rectangular dummy fills to cover the extended regions of the substrate. Finally, in FIG. 1A, overlapping rectangular dummy fills are used to address the pattern density distribution by filling the extended regions of the substrate.
A disadvantage of the conventional method and using predefined shapes is that the repeated dummy structure can be affected by the boundary-restriction effect. That is, the convention method ignores the many interferences at the boundaries of the layout structure which will restrict the placement of the dummy fill. Another disadvantage of the conventional method is the lack of density control. The insertion of uniform dummy fills creates inflexibility with respect to the dummy pattern density. Still another disadvantage is the layout dependency which will not address the lack of palanarization in the final structure. Finally, the conventional dummy insertion algorithm will result in the asymmetric dishing effect and Rs variation (board level simulation result) which can be as large as 7% for the future generation having gate length of less than 65 nm.
Additionally the repeated dummy shapes and different dimensions of the dummy structures lack density control around the circuit pattern and smart dummy fill approach. These and other drawbacks reduce the dummy fill's ability to effectively control the process variations caused by the proceeding CMP processes.